1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit provided with an inter-layer insulating film formed between a lower wiring layer and an upper wiring layer.
2. Description of the Prior Art
As is well known, there is a great tendency increase the degree of integration of semiconductor integrated circuits including bipolar transistors as the principal elements, such as memory large-scale integrated (LSI) circuits or logic LSI circuits. To this end, a bipolar transistor developed by the inventors of the present invention has a side wall base contact structure (SICOS) as stated, for example, in Japanese patent Application No. 59-225738. In this bipolar transistor, a base region is formed in a convex land region formed in an active region, and a base electrode is connected to the base region on the side wall of the convex land region. That is, the bipolar transistor having the SICOS diminishes the area of the base region by a decrement corresponding to an area for connecting the base region and the base electrode to increase the degree of integration.
The semiconductor integrated circuit being developed by the inventors of the present invention has a multilayer interconnection (multilayer aluminum interconnection) structure. In such a multilayer interconnection structure, the shape of steps in the lower wiring layer grows with the formation of the upper wiring layers to reduce the step coverage of the upper wiring layer. Reduction in step coverage diminishes the sectional area of wiring lines in the upper wiring layer, and thereby the resistance of the wiring lines is increased and breakage of the wiring lines is caused.
Lines are arranged automatically in the wiring region of the logic LSI circuit by a computer-aided automatic wiring layout (DA) method. The automatic wiring layout method extends lines in specified regions among grid wiring channel regions, namely, a plurality of rows of first wiring channel regions extending along the direction of lines and a plurality of lines of second wiring channel regions extending along the direction of rows. The lines of each layer extend respectively only in the wiring channel regions and, in some cases, it is possible that the lines of a plurality of layers are superposed in the wiring channel regions at the same position. Consequently, the shapes of the steps in the logic LSI circuit of the multilayer interconnection structure are enlarged.
When the automatic wiring layout method is employed, a dummy pedestal method effectively suppresses the enlargement of the shapes of steps in the lower wiring layer. The dummy pedestal method forms a plurality of lower wirings having a basic, rectangular short pattern previously in the first wiring channel region of a wiring region. The plurality of lower wirings are arranged at predetermined intervals along the direction of lines (a direction along which the lines are extended). The lower wiring is shifted by half a pitch relative to the lower wiring of an another adjacent first wiring channel region. Since the lines of the lower wiring layer are used for wiring or dummy pedestals, the lower wiring has a predetermined large size along the direction of lines. That is, the lines (basic short pattern) of the lower wiring layer are formed uniformly in the wiring forming region, and hence irregularity in the height of steps in the surface of a layer insulating film is reduced. The lines in the lower wiring layer are connected by the lines of the upper wiring layer through connecting holes formed in the inter-layer insulating film at positions corresponding to the junctions of the lines of the lower wiring layer. The lines of the upper wiring layer extend in the second wiring channel along the direction of lines. That is, in such a wiring system formed by the dummy pedestal method, signals are transferred by the lines of the lower wiring layer connected by the lines of the upper wiring layer, and the rest of the lines of the lower wiring layer not connected by the lines of the upper wiring layer are used as dummy pedestals.